DIR-V VEGA Microprocessor
DIR-V VEGA Microprocessors is a series of indigenous microprocessors developed by C-DAC, MeitY, Govt. of India under the Digital India RISC-V (DIR-V) program. The VEGA series comprises of 32/64-bit Single/Dual/Quad Core superscalar Out-of-Order high performance processors based on RISC-V Instruction Set Architecture. The first VEGA processor based SoC chip THEJAS32, a 32-bit Single core SoC has been successfully fabricated. A fully indigenous and “Made in India” ARIES development platform based on THEAJS32 chip has been made widely available, targeted for both industry and academia involving embedded system design and IoT applications.
About the event
The DIR-V VEGA nationwide roadshow, jointly organized by IEEE India Council and C-DAC, MeitY, will be held concurrently at various centers across India. This comprehensive training program, encompassing hands-on sessions, offers a deep dive into the VEGA series of processors and their ecosystem. The training covers both theoretical foundations and practical applications, including insights into ARIES development boards, SDK utilization, and application development. Experts from C-DAC, integral members of the VEGA Processor development team, will deliver the training sessions. This workshop is designed for a diverse audience, including students, faculty members, research scholars, and industry professionals. Certificates will be awarded upon successful completion of the workshop.
Agenda
- Central Inauguration of Roadshow from MeitY
- Technical Sessions from Industry Experts
- Two-day hands-on workshop on the VEGA Processor and Ecosystem
- Familiarization of the ARIES development board and sensor interfacing
- Demonstration of IoT application modules developed during the workshop
- Display and screening of cost-effective solutions developed using VEGA ecosystem
How can you Attend?
The roadshow is open to a diverse range of participants, including students, research scholars, faculty members, and industry professionals who are eager to explore indigenous microprocessors and their capabilities.
- Student
- Research Scholar
- Faculty
- Industry professional
Registration link
Scan the QR code or Click here
Regional Venues
Important dates
Stage | Timeline |
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Last Date for Participants to Register for workshop: | 30th October 2023 |
Announcement of the First List of Participants: | 27th October 2023 |
Last date for Paying Registration Fee: | 30th October 2023 |
Announcement of the Second List of Participants: | 31st October 2023 |
Last date for Paying Registration Fee: | 3rd November 2023 |
Nationwide VEGA Workshop at Regional Venues | 17th November – 18th November 2023 |
Certificate Distribution to Participants: | 30th November 2023 |
Organizing Team | |
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Mr. Krishnakumar Rao S raokk@cdac.in Program Manager, Digital India RISC-V Program, Scientist G, Group Head, Hardware Design Group, C-DAC Trivandrum |
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Mr. Libin T. T libin@cdac.in , 9895060576 Scientist F, Hardware Design Group, C-DAC Trivandrum Industry Member-IAYPSC,IEEE India Council |
Dr. John Jose johnjose@iitg.ac.in, 9048665842, Associate Professor, Department of CSE, IIT Guwahati Vice-Chair, IEEE India Council |
Mrs. Neetha Maria Celin neetha@cdac.in, 9895372193 Scientist E, Hardware Design Group C-DAC Trivandrum |
Dr. Ruchika Gupta ruchikae7396@cumail.in, 8511105298 Professor, Department of CSE Chandigarh University Secretary-IAYPSC, IEEE India Council |