DIR-V VEGA Microprocessor

DIR-V VEGA Microprocessors is a series of indigenous microprocessors developed by C-DAC, MeitY, Govt. of India under the Digital India RISC-V (DIR-V) program. The VEGA series comprises of 32/64-bit Single/Dual/Quad Core superscalar Out-of-Order high performance processors based on RISC-V Instruction Set Architecture. The first VEGA processor based SoC chip THEJAS32, a 32-bit Single core SoC has been successfully fabricated. A fully indigenous and “Made in India” ARIES development platform based on THEAJS32 chip has been made widely available, targeted for both industry and academia involving embedded system design and IoT applications.

About the event

The DIR-V VEGA nationwide roadshow, jointly organized by IEEE India Council and C-DAC, MeitY, will be held concurrently at various centers across India. This comprehensive training program, encompassing hands-on sessions, offers a deep dive into the VEGA series of processors and their ecosystem. The training covers both theoretical foundations and practical applications, including insights into ARIES development boards, SDK utilization, and application development. Experts from C-DAC, integral members of the VEGA Processor development team, will deliver the training sessions. This workshop is designed for a diverse audience, including students, faculty members, research scholars, and industry professionals. Certificates will be awarded upon successful completion of the workshop.

Agenda

  • Central Inauguration of Roadshow from MeitY
  • Technical Sessions from Industry Experts
  • Two-day hands-on workshop on the VEGA Processor and Ecosystem
  • Familiarization of the ARIES development board and sensor interfacing
  • Demonstration of IoT application modules developed during the workshop
  • Display and screening of cost-effective solutions developed using VEGA ecosystem


How can you Attend?

The roadshow is open to a diverse range of participants, including students, research scholars, faculty members, and industry professionals who are eager to explore indigenous microprocessors and their capabilities.

  • Student
  • Research Scholar
  • Faculty
  • Industry professional

Registration link


Scan the QR code or Click here 


Regional Venues

Sl No.Name of the Regional VenuePlaceContact PersonEmail AddressMobile NoBrochure
1Alliance UniversityBangalore, KarnatakaDr.Harinath Aireddyharinath.aireddy@alliance.edu.in9475175218
2Amrita University Bengaluru CampusBangalore, KarnatakaNavin Kumarnavinkumar@ieee.org9019930325
3Birla Institute of Technology and Science-Pilani Hyderabad, TelanganaSoumya J soumyaj@hyderabad.bits-pilani.ac.in9490722295
4Chandigarh UniversityMohali, PunjabAleem Alialeem.e12948@cumail.in9548649120
5Cochin University of Science and TechnologyCochin, KeralaRekha K Jamesrekhajames@cusat.ac.in9745182001
6Guru Tegh Bahadur Institute of TechnologyRajouri Garden, DelhiMukesh Sahumukeshsahu@ieee.org 9212425434
7Indian Institute of Information Technology Bhopal Bhopal, Madhya PradeshGaurav Kumar Bhartigkbharti.iiitbhopal@gmail.com9864084143
8KIET Group of InstitutionsGhaziabad, Uttar PradeshDr.Deepak Singhdeepak.singh@kiet.edu9412282526
9Koneru Lakshmaiah UniversityGuntur, Andhra PradeshA.Pandianpands07@gmail.com9940958638
10Mody University of Science and TechnologySikar, RajasthanJeetu Sharmajeetusharma.cet@modyuniversity.ac.in9610598495
11Netaji Subhash Engineering CollegeKolkata, West BengalTridibesh Nagtridibeshnag@gmail.com9831234264
12PSG College of TechnologyCoimbatore, Tamil NaduP Saravanandps.ece@psgtech.ac.in9894412300
13Thakur College of Engineering and TechnologyMumbai, MaharashtraDr.Lochan Jollylochan.jolly@thakureducation.org9821991509
14Vardhaman College of EngineeringHyderabad, TelanganaSangeeta Singhsangeeta.singh@ieee.org 9505889283
15Vellore Institute of Technology (VIT) ChennaiChennai, TamilnaduVydeki Dchennai.asstdiror@vit.ac.in9600005340

Important dates

StageTimeline
Last Date for Participants to Register for workshop:30th October 2023
Announcement of the First List of Participants:27th October 2023
Last date for Paying Registration Fee:30th October 2023
Announcement of the Second List of Participants:31st October 2023
Last date for Paying Registration Fee:3rd November 2023
Nationwide VEGA Workshop at Regional Venues17th November – 18th November 2023
Certificate Distribution to Participants:30th November 2023

Organizing Team
Mr. Krishnakumar Rao S
raokk@cdac.in
Program Manager, Digital India RISC-V Program,
Scientist G, Group Head,
Hardware Design Group, C-DAC Trivandrum
Mr. Libin T. T
libin@cdac.in , 9895060576
Scientist F, Hardware Design Group,
C-DAC Trivandrum
Industry Member-IAYPSC,IEEE India Council
Dr. John Jose
johnjose@iitg.ac.in, 9048665842,
Associate Professor, Department of CSE, IIT Guwahati
Vice-Chair, IEEE India Council
Mrs. Neetha Maria Celin
neetha@cdac.in, 9895372193
Scientist E, Hardware Design Group
C-DAC Trivandrum
Dr. Ruchika Gupta
ruchikae7396@cumail.in, 8511105298
Professor, Department of CSE
Chandigarh University
Secretary-IAYPSC, IEEE India Council