C-DAC has successfully completed the design, development and validation of a series of 32-bit /64-bit Single and Multi-core superscalar Out-of-Order high performance processors named ‘VEGA’, based on the open source RISC-V Instruction Set Architecture (ISA) with Multilevel Caches, Memory Management Unit and Coherent Interconnect. C-DAC has also integrated a wide range of in-house developed Silicon proven System and Peripheral IPs and has successfully ported the SoCs on FPGA boards, booted Linux/ FreeRTOS, run various applications and verified the performance with standard benchmarks. The complete software ecosystem comprising of the Board Support Packages, SDK with integrated tool chain, IDE plug-ins and Debugger for development, testing and debugging is also available.

As part of the स्वदेशी Microprocessor Challenge, C-DAC will make available two VEGA series microprocessors and ecosystem for participants to choose based on their requirements and target application.

  1. VEGA ET1031, a 32-bit high performance microcontroller class processor comprising of a 3-stage in-order RISC-V based core. This processor design is compact and efficient and is targeted for applications like sensor fusion, smart meters, small IoT devices, wearable devices, electronic toys, etc. The peripherals available in VEGA ET1031 processor based SoC (THEJAS32) are GPIO, Interrupt Controller, Timers, RAM, SPI, UART, I2C, PWM and ADC. This SoC is targeted for Arty A7-35T FPGA board.
  2. VEGA AS1061, a 64-bit processor with a 6-stage in-order pipeline optimized for high performance. This processor comprises of an efficient branch predictor and Instruction & Data caches and is targeted for applications like IoT devices, motor control, wearable devices, high-performance embedded, consumer electronics and industrial automation. The peripherals available in this VEGA AS1061 processor based SoC (THEJAS64) are GPIO, Interrupt Controller, Timers, DDR3 RAM, SPI, UART, I2C, PWM, ADC and 10/100 Ethernet. This SoC is targeted for Arty A7-100T FPGA board.
  3. Given below are the features of these two processor cores and the list of peripherals supported in the SoC.

CPU Cores

Key FeaturesVEGA ET1031VEGA AS1061
RISC-V ISARV32IMRV64IMAC
No of cores11
PipelineIn-OrderIn-Order
Pipeline Stages3-Stage6-Stage
Processor modesMachineMachine/Supervisor/User
MMUNoYes
DebugOptionalYes
Branch PredictorNoYes
L1 ICaches192 KB TIMIcache 8KB, Dcache 8KB

SoC Details

SoC DetailsTHEJAS32THEJAS64
ProcessorVEGA ET1031VEGA AS1061
DRAM-256MB
SRAM192KB128KB
Ethernet-10/100
GPIO3232
Interrupt ControllerYesYes
Timers33
SPI33
UART33
PWM88
I2C22
ADC4-channels4-channels

Deliverables:

    The participants will be provided with the following material for the challenge.

  • FPGA development board by MeitY
  • Documentation about the RISC-V Processors.
  • MCS/bit files for FPGA board
  • Links to Git repositories containing SDK and sample applications
  • Linux port for the 64-bit processor
  • User guide and tutorials