The Microprocessor Development Programme (MDP) is initiated and funded by the Ministry of Electronics and Information Technology (MeitY), Govt. of India with the mission objective to design and develop indigenously, a family of Microprocessors, related IPs and the complete ecosystem to enable fully indigenous product development that meets various requirements in the strategic, industrial and commercial sectors.
The project has been conceived considering the growing need in India to attain self-sufficiency in many sectors, especially in the electronics sector. As an emerging super power, India is growing rapidly and automation and digitalization plays a vital role. The digital technologies are heavily dependent on electronic devices which are either imported or built on parts originating from foreign countries. The Microprocessors which form the core component of any electronic equipment are entirely imported from foreign countries.
During the early ages of the digital era, the security threats were mainly on software platforms. But, these days the hardware is being targeted and the threat level is far more disastrous than at the software level, because of the device complexity and irreversibility. In the backdrop of security concerns over electronic devices manufactured abroad, MeitY has launched this project to promote the development of indigenous microprocessors.
Major benefits of an indigenous microprocessor includes improved security as the design is fully transparent, capability to effectively over come sanctions imposed on import of complex technology, cost-effective solutions, nurture the nascent fabless service and startups in this high technology domain.
As part of the Microprocessor Development Programme, C-DAC has successfully completed the development of the VEGA series of microprocessors in soft IP form, viz. 32-bit single-core (in-order), 64-bit single-core (in-order & out-of-order), 64-bit dual-core (out-of-order), and 64-bit quad-core (out-of-order). These high performance processors are based on the open source RISC-V Instruction Set Architecture with Multilevel Caches, Memory Management Unit and Coherent Interconnect.
Multiple SoCs based on these processors are in advanced stage of ASIC implementation. A 64-bit single core processor based SoC and a 64-bit dual core processor based SoC will be taped out first followed by a 64-bit quad core processor based SoC. The proposed SoCs will be realized, integrating in-house developed silicon proven peripheral IP targeting various applications. Strategic, Industrial, Automotive, Health, Consumer, etc are some of the application areas.
The complete software ecosystem comprising of the Board Support Packages, SDK with integrated tool chain, IDE plug-ins and Debugger for development is also available.