C-DAC has a wide range of System and Peripheral IPs under the brand name ASTRA which are Silicon proven, comprises of the robust RTL, extensively verified and fully synthesizable technology independent IP cores which form the building blocks for an SoC implementation.

These IP cores are provided with the complete RTL source code, standalone test benches, verification suites, synthesis and test scripts and complete documentation.

Key Features

• Portfolio of robust RTL IP
• Emphasis on quality
• Well documented
• Extensively verified to ensure functional integrity
• Fully synthesisable

ASTRA IP Cores

EROTG1 - USB On-the-Go controller

• Compliant to USB2.0 and UTMI+ specifications
• Supports Host Negotiation and Session Request Protocols
• True dual role capability
• Full speed and High speed support

ERUSBHC - USB Host Controller

• Compliant to USB2.0 and UTMI+ specifications
• Adapted EHCI Standard
• True dual role capability
• Full speed and High speed support
• Generic Microprocessor Interface

ERUSB2 - USB Function controller

• Compliant to USB2.0 and UTMI specifications
• Full speed and high speed modes
• Upto 7 IN and 7 OUT end points other than control
• Supports all USB Transfer modes

ERPCIe - PCI Express Endpoint Controller

• Compliant with PCI Express 2.0 base specification
• Architecture Supports x1 2.5/5 Gbps lane configuration
• Standard 16-bit PIPE Interface for PHY
• Supports configurable multiple traffic classes on one or more virtual channels
• Advanced Error reporting support

ERSATAII - SATA Host Controller

• Compliant to Serial ATA 2.6 specification
• 1.5 Gbps and 3.0 Gbps speeds
• Integrated SATA link layer and transport layer logic
• Native Command Queuing (NCQ)
• Supports 31 outstanding commands

ERMAC - Ethernet Media Access Controller (10/100 Mbps)

• Compliant with IEEE 802.3/802.3 x specification
• Full duplex/half duplex operation
• 8/16/32 bit generic host interface
• Supports MII for PHY
• Supports perfect and imperfect address filtering for multicast

ERGMAC - Gigabit Ethernet Media Access Controller

• Compliant with IEEE 802.3 2005 specification
• Full duplex/half duplex operation
• Jumbo Frames support upto 8KB
• Supports Gigabit MII for PHY
• Supports frame bursting
• 32-bit generic Host interface

ER15530 - Manchester Encoder Decoder core

• Supports MIL 1553 interface
• Supports bipolar configuration
• Data transfer rate of 1 Megabits/second

ERVIC - Vectored Interrupt Controller

• Support for 16 standard interrupts
• Support for 8 vectored interrupts
• Programmable INT selection
• Programmable interrupt priority level masking
• AHB mapped for faster interrupt response
• Hardware interrupt priority
• Raw interrupt status

ER146818 – Real Time Clock

• Software compatible with MC146818
• 100 year calendar
• Year 2000 compliant
• Programmable priority interrupt
• Square wave generator

ERTIMER - Timer

• Upto eight programmable timers
• Configurable timer width: 8 to 32 bits
• Configurable APB width: 8 to 32 bits
• Support for two operation modes: free-running and user-defined count
• Support for independent clocking of timers
• Configurable option for a single or combined interrupt output

ER16C450 – UART

• Software compatible with NS16C450
• Programmable wordlength, stop bits and parity
• Programmable baud rate generator
• Interrupt controller
• Loop-back mode
• Scratch register