THEJAS32 SoC

THEJAS32 SoC is based on the VEGA ET1031 processor, which is a 32 bit single core in-order, 3-stage pipeline processor. This processor is based on the open source RISC-V Instruction Set Architecture and operates at a frequency of 100MHz. The SoC also includes peripherals like 256KB internal SRAM, Three UARTs, Four SPIs, Three TIMERs, Eight PWMs, Three I2C interfaces, 32 GPIOs etc. This SoC is designed and developed by Centre for Development of Advanced Computing (C-DAC) as part of the Digital India RISC-V (DIR-V) Program, by the Ministry of Electronics and Information Technology, Government of India.

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