VEGA MICROPROCESSORS
C-DAC is executing the Microprocessor Development Programme initiated and funded by MeitY with the mission objective to design and develop indigenously, a family of Microprocessors, related IPs and the complete ecosystem to enable fully indigenous product development that meets various requirements in the strategic, industrial and commercial sectors.As part of the project C-DAC has successfully developed VEGA series of microprocessors in soft IP form, viz. 32-bit single-core (in-order), 64-bit single-core (in-order & out-of-order), 64-bit dual-core (out-of-order), and 64-bit quad-core (out-of-order). These high performance processors are based on the open source RISC-V Instruction Set Architecture with Multilevel Caches, Memory Management Unit and Coherent Interconnect. The Processor IP have been integrated with a wide range of indigenously developed Silicon proven system and peripheral IPs and ported on FPGA development platforms, Linux/FreeRTOS ported, and performance demonstrated by benchmarking and executing various applications. Face detection, object detection, seamless image merging, and media server are some of the applications successfully ported. Also, Linux with X-Windows (GUI based Linux) and Network File System (NFS) was booted successfully with monitor, keyboard, and mouse interfaced to the 64-bit single-core processor ported on FPGA Development Platform.
The proposed SoCs will contain dual/quad core processor as the processing part integrated with in-house developed silicon proven peripheral IP suitable for various applications. Strategic, Industrial, Automotive, Health, Consumer, etc are some of the application areas.
| Key Features | VEGA ET1031 | VEGA AT1051 | VEGA AS1061 | VEGA AS1161 | VEGA AS2161 | VEGA AS4161 |
|---|---|---|---|---|---|---|
| RISC-V ISA | 32-bit RV32IM | 32-bit RV32IMAFC | 64- bit RV64IMAFDC | 64-bit RV64IMAFD | 64-bit RV64IMAFD | 64-bit RV64IMAFD |
| No of cores | 1 | 1 | 1 | 1 | 2 | 4 |
| Pipeline | In-order | In-order | In-order | Out-of-Order | Out-of-Order | Out-of-Order |
| Pipeline stages | 3-Stage | 5-Stage | 6-Stage | 13-16 Stage | 13-16 Stage | 13-16 Stage |
| Superscalar | No | No | No | Yes | Yes | Yes |
| Processor modes | Machine | Machine/ Supervisor/User | Machine/ Supervisor/User | Machine/ Supervisor/User | Machine/ Supervisor/User | Machine/ Supervisor/User |
| MMU | Optional | Yes | Yes | Yes | Yes | Yes |
| Debug | Optional | No | Yes | Yes | Yes | Yes |
| Branch Predictor | No | Yes | Yes | Yes | Yes | Yes |
| L1 ICache | TIM | 8KB | 8KB | 32KB | 32KB | 32KB |
| L1 DCache | TIM | 8KB | 8KB | 32KB | 32KB | 32KB |
| L2 Caches | No | No | No | No | 512KB | 1024KB |
| Bus Interface | AHB/AXI4 | AHB/AXI4 | AHB/AXI4 | AHB/AXI4/ACE | AHB/AXI4/ACE | AHB/AXI4/ACE |
| IEEE 754-2008 compliant FPU | No | Single precision | Single and Double precision | Single and Double precision | Single and Double precision | Single and Double precision |
| Availability | Now | Now | Now | Now | Now | Now |
The complete software ecosystem comprising of the Board Support Packages, SDK with integrated tool chain, IDE plug-ins and Debugger for development is also available.
Multiple SoCs based on these processors are in advanced stage of ASIC implementation. VEGA AS1161, a 64-bit single core processor based SoC and VEGA AS2161, a 64-bit dual core processor based SoC will be taped out first followed by VEGA AS4161, a 64-bit quad core processor based SoC. The proposed SoCs will be realized, integrating in-house developed silicon proven peripheral IP targeting various applications. Strategic, Industrial, Automotive, Health, Consumer, etc are some of the application areas.