VEGA AS1161 features an out-of-order processing engine with a 16 stage pipeline enabling it to meet next gen computational requirements. The processor also supports single and double precision floating point instructions, and MMU for Linux based applications. AS 1161 is optimized for high performance integrating an Advanced branch predictor for efficient branch execution, Instruction and Data caches. Features also include PLIC and vectored interrupts for serving various types of system events. An AXI or AHB interface enables ease of system integration and a WFI mode for power management, and JTAG debug interface for development support.
Key features
- RISC-V 64G (RV64IMAFD) Instruction Set Architecture
- 13-16 stage out-of-order pipeline implementation
- Advanced branch predictor: BTB, BHT, RAS
- Harvard architecture, separate Instruction and Data memories
- User-, Supervisor- and Machine-mode privilege levels
- Fully-featured memory subsystem with Linux support
- Memory Management Unit
- Page-based virtual memory
- Configurable L1 caches
- High-performance IEEE 754-2008 compliant floating-point unit
- AXI4- / ACE, AHB- compliant external interface
- Platform Level Interrupt Controller
- Up to 127 IRQs
- Low interrupt latency
- Vectored interrupt support
- Advanced Integrated Debug Controller
- JTAG compliant interface
- HW/SW breakpoints support
- Debug extension allowing Eclipse debugging via a GDB >> openOCD >> JTAG connection
- Linux compatible
- Zephyr compatible
- FreeRTOS port
- Storage, Smart NICs
- Edge Analytics, Data Analytics
- Autonomous Machines